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em39l v040 4m (512kx8) bit s flash memory specifica t ion general description the em39lv040 is a 4m bits flash memory organized as 512k x 8 bits. the em39lv040 uses a single 3.0 volt-only power supply for both read and write functions. featuring high performance flash memory technology, the em 39lv040 provides a typical byte-program time of 11 sec and a typical sector-erase ti me of 40 ms. the device uses toggle bit or data# pollin g to detect the compl e tion of the pr ogram or era s e ope ration. to protect again s t inadvertent write, the device has on-chip hardware and software data protection schemes. the device offers typical 10 0,000 cycl es endu ran c e a n d a greate r than 10 years d a ta retention. the em39lv040 conforms to jedec standard pin outs for x8 memories. it is offered in packa ge type s of 32 -le ad p l cc, 32-pin t s op, and kno w n g ood die (kgd). for k g d, ple a se conta c t elan micro e le ctro nics or its rep r esent atives f o r detaile d informatio n (see appendix at the bottom of this specificat ion for ordering information). the em39lv040 devices are developed for applicat ions that require memories with convenient and economical updating of program, data or configurations, e.g., networking cards, cd-rw, scanner, digital tv, electroni c books, gps, router/switcher, etc. features single pow e r supply full voltage range from 2.7 to 3.6 volts for both read and write operations regulated volt age range: 3.0 to 3.6 volts for both read and write operations sector-erase capability uniform 4kbyte sectors sector-erase capability uniform 64kbyte sectors read access time a ccess t i me : 45, 55, 70 and 90 ns pow e r consumption ac tive c u rrent : 5 ma (typical) s t andby current : 1 a (ty p ical) erase/program features sector-erase time : 40 ms (typical) chip-erase time : 40 ms (typical) byte-program time : 11 s (ty p ical) chip rewrite time : 6 seconds (typical) end-of-program or end-of-erase detection data# polling toggle bit cmos i/o compatibility jedec standard pin-out and software command sets compatible with single-power supply |flash memory high reliability endurance cycles: 100k (typical) data retention: 10 years package option 32-pin plcc 32-pin tsop this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 1 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion functional block diagram x - d e co der fl a s h m e m o ry a r ra y y- d e co der i / o b u f f er s an d d a t a la t c he s ad d r e s s bu f f e r & la t c he s c o nt r o l l o gi c me m o r y a d d r e s s ce # oe # we # dq 7 - d q 0 figure 0a: functional block diagram pin assignments 32-lead plcc 14 15 16 17 18 19 2 0 30 31 32 43 2 1 dq 1 d q 2 v ss dq3 d q4 dq5 d q6 a1 2 a 1 5 a 1 6 a 1 8 v dd we # a17 5 6 7 8 9 10 11 12 13 dq0 a7 a6 a5 a4 a3 a2 a1 a0 21 22 23 24 25 26 27 28 29 a14 a13 a8 a9 a11 oe# a10 ce # dq7 3 2 -l ea d p l c c t o p v i ew figure 0b: plcc pin assignm ents this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 2 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion 32-lead tsop s t an da r d t s o p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 oe# v ss a0 a4 a5 a6 a7 we # a8 a9 a11 a1 2 a13 a14 a1 5 v dd a1 6 a1 a2 a3 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 a10 ce# a17 a1 8 figure 0c: tsop pin assignm ents pin description pin name function a 0 ? a 1 8 1 9 a d d r e s s e s d q 7 ? d q 0 d a t a i n p u t s / o u t p u t s c e # c h i p e n a b l e o e # o u t p u t e n a b l e w e # w r i t e e n a b l e v dd 3.0 volt-only single pow er supply * v ss device ground * see appendix for ordering info rmation on speed options and volt age supply tolerances. table 1: pin description this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 3 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion device operation the em39lv040 uses commands to initiate the memory operation functions. the commands are written to the device by asse rting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read op eration of the em39lv04 0 i s contro lled b y ce# an d o e #. both have to be lo w for the syste m to obtain d a ta fr om the outputs. ce# is use d for device sele ction . when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control an d i s use d to gate data from the output pin s . the d a ta bu s is in hi gh im p edan ce state when either ce# or oe# is high. refer to the read cycle timing diagram in figure 1 for further details. by te program the em39lv040 is programmed on a byte-by-byte basis. before programming, the sector where the byte is located; must be eras ed completely. the program operation is accomplished in three steps : the first step is a three-byte load s equence for software data protection. the second step is to load byte address and byte data. during the byte program operation, the addre s ses are latched on the falli ng edg e of either ce# or we#, whicheve r occurs last; and the data is latched on the ri sing edge of either ce# or we#, whichever oc c u rs firs t. the third step is the internal program operati on which is initiated after the rising edge of the fourth we# or ce#, whichever occurs fi rst. the pro gram operation, once initiated, will be completed within 16 s. see figures 2 and 3 for we# and ce# controlled program operation timing diagrams respectively and figure 12 for the corresponding flowchart. duri ng the p r ogra m op erat ion, the only valid re ad s are data# polli n g and t oggl e bit. during the internal program operation, the host is free to perform additional tasks. any command issued during the internal program operation is ignored. this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 4 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion em39l v040 device operation operation ce# oe# we# dq address r e a d v il v il v ih d out a in p r o g r a m v il v ih v il d in a in e r a s e v il v ih v il x * sector or block address, xxh for chip-erase standby v ih x x h i g h z x w r ite inhibit x v il x h i g h z / d out x w r ite inhibit x x v ih high z / d out x softw are mode v il v il v ih see t able 3 product identification * x can be v il or v ih , but no other value. table 2: em39lv040 device operation w r ite command/command sequence the em39lv040 provides two software methods to detect the completion of a program or erase cycle i n orde r to optimize the syst em wr ite cy cl e time. the softwa r e dete c tion incl ude s two status bit s : data# polli ng (dq7) a n d toggle bit (d q6). the end-of-write detection mo de is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the writ e operation is asynchronous with the system; therefo r e, eith er a data # po lling o r to ggl e bit rea d ma y be sim u ltan eou sly co mpl e ted with the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq7 or dq6. in order to prevent such spurious rejection, whe n an e r ro neou s result occurs, the software ro utin e sh ould in clu de an a dditio nal two time s loop to read t he acce ssed l o catio n . if b o th r ead s are valid, then the device ha s completed the write cycle, otherwise the rejection is valid. chip erase the em39lv040 provides chip-erase feature, wh ich allows the entire memory array to be erased to logic ?1? state. the chip-erase oper ation is initiated by executing a six-byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase oper ation, the only valid reads are toggle bit and data# polling. see table 3 for the comm and sequence, figure 6 for timing diagram, and figure 15 for the corresponding flowchart. any command issued during the chip-erase operation is ignored. this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 5 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion sector erase the em39lv040 offers sector-erase mode. the sector-erase operation allows the system to era s e the d e vice on a se ctor-by-se ctor basi s . the se ctor a r chite c ture i s b a se d on unifo rm sector size of 4 kbyte. the sector-erase oper ation is initiated by executing a six-byte command sequence with sector-erase command (30h ) and sector address (sa) in the last bus cy cle. the se ctor o r b l ock add re ss i s la tche d on the falling edg e of the sixth we# pul se, while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined by using either data# polling or t oggle bit method. see figures 7 for timing waveforms. any command issued during t he sector-erase operation is ignored. dat a# polling (dq7) when the em39lv040 is in the internal program operation, any attempt to read dq7 will produce the complement of the true data. on ce the program operation is completed, dq7 will produce the true data. note that ev en though dq7 may have valid data immediately followin g the compl e tion of an intern al progra m ope rati on, the remai n ing data o u tputs may still be invalid (val id data on the entire data bus will appear in subsequent succ essive read cy cles after an interval of 1 s). during internal erase operation, any attempt to read dq7 will prod uce a ?0 ?. once the internal erase operatio n is completed, dq 7 will pro d u c e a ?1?. the data# pollin g is valid after the risi ng edg e of f ourth we# (or ce# ) p u lse for pro g ram operation. for sector-erase or chip-erase, the data# po lling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 4 for data# polling timing diagram and figure 13 for the corresponding flowchart. t oggle bit (dq6) during the internal program or erase operation, any consecutive atte mpts to read dq6 will prod uce alte rnating 1 s and 0s, i.e., toggl ing bet wee n 1 and 0. when the i n tern a l prog ram or erase operation is complet ed, t he dq6 bit will stop toggling. the device i s then ready for the next operatio n. the toggle bit is valid after t he risin g edge of fourth we# (or ce#) pulse for program operation. for sector-erase or chip-e rase, the toggle bit is valid after the rising edge of sixth we# (o r ce# ) pulse. see figure 5 for toggle bit timing diag ram a nd figu re 13 for the corresponding flowchart. dat a protection the em39lv040 provides both hardware and softwar e features to protect the data from inadvertent write. this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 6 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion hardw a re dat a protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a writ e cy cle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.5v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit the write operation. this prev ents inadvertent write during power-up or power-down. sof t w a re dat a protection (sdp) the em39lv040 provides the jedec approved so ftware data protection (sdp) scheme for program and erase operations. any program operation requires the inclusion of the three - byte se quen ce. the three-byte load se quen ce is used to initiate the program ope ration , providing optimal protection from inadvertent write operations, especially during the system power-up or power-down transiti on. any erase operation requires the inclusion of six-byte sequence. see table 3 below for the spec ific software command codes. during sdp command sequence, invalid commands will abor t the device to read mode within t rc . sof t w a re command sequence 1st bus write cy cle 2nd bus write cy cle 3rd bus write cy cle 4th bus write cy cle 5th bus write cy cle 6th bus write cy cle c o mmand sequence addr 1 d a t a a d d r 1 data addr 1 data addr 1 data addr 1 d a t a a d d r 1 data by te program 5555h aah 2aaah 55h 5555h a0h b a 2 data sector erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 30h chip erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h softw are id entry 4 5 5 5 5 h a a h 2 a a a h 55h 5555h 90h manufacture id 5555h aah 2aaah 55h 5555h 90h 0000h 7fh manufacture id 5555h aah 2aaah 55h 5555h 90h 0003h 7fh manufacture id 5555h aah 2aaah 55h 5555h 90h 0040h 1fh device id 5555h aah 2aaah 55h 5555h 90h 0001h 29fh softw are id ex it 5 x x h f 0 h softw are id ex it 5 5 5 5 5 h a a h 2 a a a h 55h 5555h f0h notes : 1. address format a18-a0 (hex) & address a16 can be v il or v ih , (but no other value) for the command sequence. 2. ba = program byte address. 3. sa x for sector -erase; uses a19-a12 address lines. 4. t he device does not remain in sof t w a re product id mode if pow ered dow n (see f i gure 9 for more information). 5. both sof t w a re id exit operations are equivalent. table 3: software com m and sequence this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 7 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion absolute maximum ratings note appl ied co nd iti ons gre a ter th an these s peci f i ed ratin g s ma y cause per ma nent da mag e to the devic e. t hese are stress ratings o n ly a n d f unction al o perati on of th e devic e at these cond itions or cond itions gr e a ter than th o s e defi ned in the oper atio nal secti ons of this specific ation, a r e not i m pli ed. exposur e to abso l ute maxi mu m stress r a ting co nditi on may affect device reliability. temperature under bi as .............................................................. ?55c to 125c storage temperatur e .................................................................... ?65c to 150c d.c. voltage on any pin to gr ound potentia l ............................... ?0.5 v to v dd +0. 5 v transient voltage (<20ns) on any pin to ground potential ........... ?2.0v to v dd + 2 .0v voltage on a9 pin to ground po tential ........................................... ?0.5 v to 13.2v package power dissipation capability (ta=25 * ........................................................ 50ma * output shorted for no more than one second. no more than one output shorted at a time. operating range model name range ambient temperature vdd f u ll voltage range : 2.7~ 3.6v c o m m e r c i a l 0 : 3.0~ 3.6v f u ll voltage range : 2.7~ 3.6v ac39lv040 i n d u s t r i a l ? 4 0 : 3.0~ 3.6v table 4: operating range ac conditions for testing input rise/fa ll time ........................................................................ 5ns output load .................................................................................... cl= 30pf for 45rns output load .................................................................................... cl =100pf for 70ns/90ns see figures 10 and 11 for more details. this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 8 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion dc characteristics (cmos compatible) parameter description test conditions min max unit i dd pow e r supply current read program and erase address input = v il /v ih , at f=1/t rc min, v dd =v dd max ce#= oe#= v il , we#=v ih , all i/os open ce#= w e #= v il , oe#=v ih , 20 30 ma ma i sb standby v dd current ce#= v ihc , v dd =v dd max 10 a i li i lo input leakage current output leakage current v in =gnd to v dd, v dd =v dd max v out =gnd to v dd, v dd =v dd max 1 10 a a v il v ih v ihc input low voltage input high voltage input high voltage (cmos) v dd =v dd min v dd =v dd max v dd =v dd max 0.7 v dd v dd -0.3 0.8 v v v v ol v oh output low voltage output high voltage i ol = 100 a, v dd =v dd min i oh = - 100 a, v dd =v dd min v dd -0.2 0.2 v v table 5: dc characteristics (cm o s com patible) recommended sy stem pow e r-up t i ming parameter description min unit t pu - r ead * pow e r-up to read operation 100 s t pu - w r i t e * pow e r-up to program/erase operation 100 s * t h is p a rameter is measured only for initial qualif ication and af ter a design or process change that could af fect this p a ram e ter . table 6: recom m ended system power-up tim i ng cap acit a nce (t a = 25 c, f = 1mhz, other pins open) parameter description test conditons max c i/o * i/o pin capacitance v i/o = 0 v 1 2 p f c in * input capacitance v in = 0 v 6 p f * t h is p a rameter is measured only for initial qualif ication and af ter a design or process change that could af fect this p a ram e ter . table 7: capacitance (ta = 25 reliability characteristics sy mbol parameter min specification unit test method n en d * e n d u r a n c e 1 0 , 0 0 0 cy cles jedec standard a117 t dr * data retention 10 years jedec standard a103 i lt h * latch up 100+ i dd ma jedec standard 78 * t h is p a rameter is measured only for initial qualif ication and af ter a design or process change that could af fect this p a ram e ter . table 8: reliability characteristics this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 9 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion ac characteristics read cy cle t i ming parameters 45rec 55rec 70rec 90rec sy mbol parameter min max min max min max min max unit t rc read cy cle t i me 45 55 70 0 90 ns t ce chip enable access t i me 45 55 70 90 ns t aa address access t i me 45 55 70 90 ns t oe output enable access t i me 30 30 35 45 ns t cl z * ce# low to active output 0 0 0 0 ns t olz * oe# low to active output 0 0 0 0 ns t chz * ce# high to high-z output 15 15 25 30 ns t ohz * oe# high to high-z output 15 15 25 30 ns t oh * ou tp u t h o l d from ad dre ss c han ge 0 0 0 0 n s * t h is p a rameter is measured only for initial qualif ication and af ter a design or process change that could af fect this p a ram e ter . table 9: read cycle tim i ng param e ters program/erase cy cle t i ming parameter sy mbol parameter min max unit t bp by te-program t i me 16 s t as address setup t i me 0 ns t ah address hold t i me 30 ns t cs w e # and ce# setup t i me 0 ns t ch w e # and ce# hold t i me 0 ns t oes oe# high setup t i me 0 ns t oeh oe# high hold t i me 10 ns t cp ce# pulse w i dth 40 ns t wp w e # pulse w i dth 40 ns t wp h * w e # pulse w i dth high 30 ns t cp h * ce# pulse w i dth high 30 ns t ds data setup t i me 40 ns t dh * data hold t i me 0 ns t ida * softw are id access and exit t i me 150 ns t se sector erase 60 ms t sc e chip erase 60 ms * t h is p a rameter is measured only for initial qualif ication and af ter a design or process change that could af fect this p a ram e ter . table 10: program /erase cycle tim i ng param e ter this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 10 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion timing diagrams read cy cle t i ming diagram t aa t rc t ce t oe t ol z t clz t oh t oh z t ch z high- z high- z v ih dat a v a lid d a ta v a lid a1 8~ a0 ce# oe # we # dq 7-0 figure 1: read cycle tim i ng diagram we# controlled program cy cle t i ming diagram 555 5 2 aaa 5555 ad d r t bp inter n a l prog r a m oper a t ion st arts t dh t ds t ch t cs t ah t wp t as t wp h aa 55 a0 d a t a sw 0 s w 1 sw 2 b y t e (a dd r/ da t a ) we # oe# ce # dq 7 - 0 a18~ a0 figure 2: we# controlled program cycle tim i ng diagram this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 1 1 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion ce# controlled program cy cle t i ming diagram 5555 2 a aa 55 55 ad dr t bp internal pr o g ram operati on st a r ts t dh t ds t ch t cs t ah t cp t as t cph aa 55 a0 d a t a sw 0 s w 1 s w 2 b y t e (addr/da t a ) ce# oe # we # dq7-0 a1 8~a 0 figure 3: ce# controlled program cycle tim i ng diagram dat a# polling t i ming diagram t oe s t ce t oe h t oe da t a dat a # dat a # d at a# we # oe # ce # dq7 a18~a0 figure 4: data# polling tim i ng diagram this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 12 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion t oggle bit t i ming diagram t oe s t w o read c y c l es w i th sam e outputs t ce t oe t oe h we # oe # ce # dq6 a18~ a0 figure 5: toggle bit tim i ng diagram we# controlled chip-erase t i ming diagram note : th i s devi c e al s o sup por ts c e # contr o l l ed c h i p - e r a se oper ati on. th e w e #an d c e # si gnal s ar e i n ter c hage abl e as l ong as m i ni m u m ti m i ngs ar e m e t. ( s ee tab l e 10 ) six- by te code f o r chip- e r a s e t sc e t wp 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 sw 0 s w 1 sw 2 s w 3 sw 4 s w 5 ce# oe# we # dq7 - 0 a18~ a0 figure 6: we# controlled chip-erase tim i ng diagram this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 13 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion we# controlled sector-erase t i ming diagram six - by t e co de f o r blo c k - e r as e t se t wp 5555 2aa a 5555 5555 2a aa sa x aa 55 80 aa 55 50 s w 0 s w 1 sw 2 s w 3 sw 4 s w 5 ce # oe # we # dq 7 - 0 note: t h i s dev i ce a l s o s uppor ts ce# c ontr o l l ed sec t or - e r a s e oper ati on. t he w e #and ce # si gnal s a r e inter c hageabl e as l ong as m i ni m u m ti m i ngs ar e m e t. ( s ee t abl e 10) sa x = s ector a ddr ess x can be v il or v ih , but n o other v a lue. a18~ a0 figure 7: we# controlled sector-erase tim i ng diagram software id entry/exit and read sof t w a re id entry and read 5 555 2a a a 5555 aa 55 90 thr ee- b y t e s e q u enc e for so f t w a r e i d en t r y t wp t wp h t id a t aa sw 0 s w 1 s w 2 a ddr es s a 14- 0 ce # oe # we # dq 7 - 0 29 h 0000 h 0 0 03h 0 0 4 0 h 000 1h 7f 7f 1 f figure 8: software id entry and read this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 14 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion sof t w a re id exit and reset 555 5 2 a a a 5555 t h r ee- by t e s e q uenc e f o r s o f t w ar e i d e x i t and r e s e t a d dr es s a14- 0 t wp t wp h t id a ce # oe # we # aa 55 f0 dq 7 - 0 sw 0 s w 1 s w 2 figure 9: software id exit and reset ac input/output testing ac input/output reference w aveforms v it v ot v ih t v il t inp u t o utput r e f e r enc e p o ints note : v it = vinput t e s t v ot = vou t put t e s t v ih t = vinput h i g h t e s t v il t = vinput l o w t e s t a c tes t i n puts ar e dr i v en at v ih t (0.9 v dd ) f o r a logic " 1 " and v il t ( 0 .1 v dd ) f o r a logic " 0 ". meas u r e m e n t r e f e r enc e points f o r in puts a nd out pputs ar e v it ( 0 .5 v dd ) and v ot ( 0 .5 v dd ) . inpu t ris e and f a l l ti m e ( 1 0% - 90% ) i s < 5 ns figure 10: ac input/output reference waveform s this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 15 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion an ac t est load example c l to te s t e r to d u t figure 11: an ac test load exam ple flow charts by te-program algorithm st a r t load d a t a : a a h a ddr es s: 5 555h load d a t a : 55h ad d r e s s : 2 aaah load d a t a : a 0 h a ddr es s: 5 555h load b y t e a ddr es s/ b y t e d a t a w a i t f o r end o f p r ogr am (t bp , d a t a# p o l l i n g bi t , or t o ggl e bi t op er at i on) p r ogr am c o m p l e t e d figure 12: byte-program algorithm flowchart this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 16 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion w a it options p r o g rm /e ra s e i n it ia te d wa i t t bp , t sc e , t se or t be p r o g rm /e ra s e co m p l e t e d i n t e r nal t i m e r p r o g rm /e ra s e in i t i a t e d r ead b y t e r ead s a m e by t e p r o g rm /e ra s e co m p l e t e d ye s no to g g l e bi t p r o g rm /e ra s e in i t i a t e d r ead dq 7 p r o g rm /e ra s e co m p l e t e d yes no d a t a # p o llin g d oes d q 6 ma t c h ? i s d q 7= t r ue da t a ? figure 13: wait options flowchart this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 17 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion sof t w a re id commands l o a d d a ta : a a h a d d r es s : 55 55 h lo a d d a t a : 55 h a d dr es s : 2 a a a h lo a d d a t a : 90 h a d d r es s : 55 55 h wa i t t id a r e a d s o f t w a re id lo ad d a t a : a a h a d d r ess: 5 5 55 h lo ad d a t a : 5 5 h a d d r ess: 2 a a a h lo ad d a t a : f 0 h a d d r ess: 5 5 55 h wa i t t id a l o a d d a ta : f 0 h a d d r es s : xxh wa i t t id a r e tu rn to n o r m a l op e r a t i o n r e tu rn to n o rm a l op e r a t i o n so f t wa r e i d en t r y com m a nd seq u en c e so f t w a r e i d ex i t co mm a n d s e q uen c e x can be vil or vih, but no other value. figure 14: software id com m and flowcharts this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 18 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion erase command sequence load dat a : a a h a ddr e s s : 55 55 h load dat a : 55 h a ddr es s : 2a a a h load dat a : 80 h a ddr e s s : 55 55 h load dat a : a a h a ddr e s s : 55 55 h load dat a : 55 h a ddr es s : 2a a a h load dat a : 10 h a ddr es s : 5555 h wa i t t sce chi p e r a s ed t o ff h l o a d d a ta : a a h a d dr es s : 5 555h lo ad d a t a : 55h a d dr e ss: 2a a a h lo ad d a t a : 80h a d dr es s : 5 555h l o a d d a ta : a a h a d dr es s : 5 555h lo ad d a t a : 55h a d dr e ss: 2a a a h lo ad d a t a : 30h addr es s : s a x wa i t t se s e c t o r e r a s e d to f f h ch i p - e r a s e c o m m a nd s e que n c e s e c t o r-e ra s e c o m m and s e q uenc e x can be vil or vih, but no other value. figure 15: erase com m and sequence flowchart this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 19 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion appendix ordering informa t ion (s t a ndard product s ) the order number is defined by a comb ination of the following elements. e m 3 9 l v 0 4 0 - 7 0 f m c description temperature range (1 digit) c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package ty pe (1-3 digit) m = t s op (t y pe 1, die up, 8mm x 14mm) l = 32-pin plcc h = chip form d = know n good dice (for w a fer dice sell) f = pb (l ead ) free p ackag e speed option (2-3 digits) 45r = 45ns 55 = 55ns 70 = 70ns 90 = 90ns ** = vdd = 2.7~ 3.6v f u ll voltage range **r = vdd = 3.0~ 3.6v regulated voltage range dev i ce number/description em39lv040 4 megabit (512k x 8-bit) f l ash memory this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 20 of 21
em39l v040 4m (512kx8) bit s flash memory specifica t ion ordering informa t ion (non-s t andard product s ) for known good dice (kgd), please contact el an microelectronics at the following contact information or its representatives. el an microelectronics c o rpora t ion he a dqua rte r s : no. 12, innovation road 1 science-based industrial park hsinchu, t a iwan, r.o.c. 30077 tel : +886 3 563-9977 fa x : +886 3 563-9966 http://www .em c .com .tw hong kong: elan (hk) micro e lectro n i cs corpora t ion, lt d. rm. 1005b, 10/f empire centre 68 mody road, t s imshatsui kowloon , hong kong tel : +852 2723-3376 fax: +852 2723-7780 elanhk@emc.com.hk usa : ela n informa tion t e c hnology group 1821 saratoga a v e., suite 250 saratoga, ca 95070 usa tel : +1 408 366-8223 fax: +1 408 366-8220 europe : elan micro e lectro n i cs co rp . (europe ) dubendorfstrasse 4 8051 zurich, switzerland tel : +41 43 299-4060 fax: +41 43 299-4079 http://www. elan-europe. c om sh en zh en : ela n (she nzhe n) micro e lectro n i cs c o r p . , l t d . ssmec bldg., 3f , gaoxin s. a v e. shenzhen hi-t ech industrial park shenzhen, guandong, china tel : +86 755 2601-0565 fax: +86 755 2601-0500 sha ngha i: ela n ele c t ronic s (sha ngha i) corpora t ion, lt d. 23/bldg. #1 15 lane 572, bibo roa d zhangjiang hi-t ech park shanghai, china tel : +86 021 5080-3866 fa x : +86 021 5080-4600 this specification is subj ect to cha nge without fu rth e r notice. (07.2 2 . 2004 v1.0) page 21 of 21

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